← 返回 JSSC 论文列表JSSC 2011第2期Data Converters0.13μmCDR
A 1040-Gbs All-Digital CDR With 10-ps Period Resolution DCO and Adaptive Proport
设计了一种全数字时钟数据恢复电路，具有宽频带多相时钟和自适应比例增益控制。
0.13μm CMOS, 1.2V, 1.0-4.0 Gb/s, 3.59 ps抖动, 11.4 mW功耗
全数字时钟数据恢复数字控制振荡器自适应比例增益控制低抖动高速接口
▸采用数字控制电阻的宽频带多相时钟生成
▸自适应比例增益控制器优化抖动性能
▸数字频率捕获环路缩短捕获时间
Abstract
ber , IEEE, Deok-Soo Kim , Student Member , IEEE, Do-Hwan Oh,
Suhwan Kim, Senior Member , IEEE, and Deog-Kyoon Jeong , Senior Member , IEEE
Abstract—This paper describes the design and implementa-
tion of an all-digital clock and data recovery circuit (ADCDR)
for multigigabit/s operation. The proposed digitally-controlled
oscillator (DCO) incorporating a supply-controlled ring os-
cillator with a digitally-controlled resistor (DCR) generates
wide-frequency-range multiphase clocks with fine resolu