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JSSC 2011第2期Other90nm

Automatic Compensation of the V oltage Attenuation in 3-D Interconnection Based

提出一种补偿3D电容耦合电压衰减的自动校准架构
90nm CMOS, 1mW/3.6mW功耗, 10%增益误差
3D集成电容耦合电压补偿系统级封装可变增益放大器
基于校准通道的电压衰减补偿方案
支持模拟和数字信号传输的3D集成技术
采用90nm CMOS工艺的面对面堆叠实现
Abstract
li , Member , IEEE, Antonio Gnudi, Federico Natali, Mauro Scandiuzzo, Roberto Canegallo, and Roberto Guerrieri Abstract—An architecture to compensate the voltage attenua- tion introduced by 3-D capacitive coupling is proposed. The scheme is based on a calibration channel which sets the gain of the variable gain amplifiers of the signal channels in such a way as to compen- sate for the voltage attenuation. Based on this architecture, a pro- totype has been designed aimed at demonstrating that 3-D