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A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline CCB Cell Daisabur
提出一种新型梯形FeRAM架构，采用电容耦合位线单元，解决干扰问题并提升读写速度。
100MHz, 10ns读写周期, 8ns访问时间, 150°C工作温度
铁电存储器梯形架构电容耦合位线抗干扰高速读写
▸梯形FeRAM架构通过短路铁电电容两极解决干扰问题
▸采用厚M3分流路径和分布式M3板线减少板线驱动延迟
▸引入激活虚拟位线及其感放消除位线间耦合噪声
Abstract
nd Tohru Ozaki
Abstract—This paper proposes a new ladder FeRAM ar-
chitecture with capacitance-coupled-bitline (CCB) cells for
high-end embedded applications. The ladder FeRAM architecture
short-circuits both electrodes of each ferroelectric capacitor at
every standby cycle. This overcomes the fatal disturbance problem
inherent to the CCB cell, and halves read/write cycle time by
sharing a plateline and its driver with 32 cells in two neighboring
ladder blocks. This configuration realizes small 0