← 返回 JSSC 论文列表JSSC 2011第3期Data Converters65nmDAC
A Continuous Time Multi-Bit 16ADC Using Time Domain Quantizer and Feedback Eleme
提出一种基于PWM和TDC的三阶连续时间ΔΣ ADC，采用65nm CMOS工艺实现。
65nm CMOS, 10.5mW, 0.15mm², 68dB DR, 20MHz BW
模数转换连续时间ΔΣ调制器时间数字转换器低功耗
▸使用PWM生成器和TDC替代多比特量化器和反馈DAC
▸TDC实现50级二进制输出，无需校准或动态元件匹配
▸在20MHz带宽下实现68dB动态范围
Abstract
mbhir , Member , IEEE ,
Mohamed M. Elsayed , Student Member , IEEE , Edgar Sánchez-Sinencio , Fellow, IEEE ,
Jose Silva-Martinez, Senior Member , IEEE, Chinmaya Mishra , Member , IEEE, Lei Chen, and
Erik J. Pankratz, Student Member , IEEE
Abstract—A third-order CT /1/6 ADC that replaces the
multi-bit quantizer and feedback DAC by a pulsewidth modu-
lation (PWM) generator and time-to-digital converter (TDC) is
implemented in 65 nm CMOS technology. The TDC provides a
50-level binary output code an