← 返回 JSSC 论文列表JSSC 2011第3期Clocking & PLLs65nmPLLClock Generation
A Wideband 36 GHz Digital 16Fractional-N PLL With Phase Interpolation Divider an
提出了一种用于4G通信标准的宽带36 GHz数字分数N频率合成器，具有低分数杂散和高线性度。
3.0–3.6 GHz频率范围，40 MHz参考频率，40 Hz分辨率，104-dBc/Hz相位噪声，3.2 MHz最大环路带宽，80 mW功耗，0.4 mm²面积
分数N频率合成器相位插值器动态元素匹配相关算法低分数杂散
▸采用基于相位插值器的分数N分频器
▸使用动态元素匹配算法提高TDC线性度
▸提出相关算法校正相位插值器失配
Abstract
r , IEEE, Salvatore Levantino , Member , IEEE, Carlo Samori , Senior Member , IEEE, and
Andrea L. Lacaita , Fellow, IEEE
Abstract—A digital /1/6 fractional-N frequency synthesizer
for 4G communication standards is presented which is able to
achieve wide loop bandwidth while producing low fractional
spurs. The loop adopts a fractional-N divider based on a phase
interpolator, allowing to shrink the TDC dynamic range and to
improve its linearity. A dynamic-element matching algorithm
is employed to