JSSC 2011第3期Memory90nmSRAM

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation C

提出一种基于P-P-N结构的10T SRAM单元，适用于低泄漏和亚阈值电压操作。

285 mV超低工作电压，16 Kb SRAM测试芯片

SRAM亚阈值操作低功耗工艺变异位线泄漏

▸创新点1：P-P-N交叉耦合反相器对结构（电路创新）。该结构通过采用P-P-N型晶体管组合形成交叉耦合反相器，显著提升了亚阈值电压下的噪声容限，支持低至285 mV的工作电压，同时增强了对工艺波动的鲁棒性。

▸创新点2：超低单元泄漏（电路创新）。通过优化晶体管堆叠和栅极偏置技术，将静态功耗降低至传统10T SRAM单元的1/3以下，特别适合超低功耗应用场景。

▸创新点3：高抗数据依赖性位线泄漏能力（系统创新）。采用独特的位线隔离设计，消除了数据相关泄漏对长位线阵列的影响，使16 Kb宏单元在90 nm工艺下仍能保持高密度集成。

▸创新点4：双模式噪声容限提升（方法创新）。在保持状态和读取操作中分别通过动态反馈和预充电控制策略，使静态噪声容限(SNM)和读取噪声容限(RNM)均提升40%以上。

Abstract

SRAM has been under its renovation stage recently, aiming to withstand the ever-increasing process variation as well as to support ultra-low-power applications using even subthreshold supply voltages. We present in this paper a novel P-P-N-based 10T SRAM cell, in which the latch is formed essentially by a cross- coupled P-P-N inverter pair. This type of cell can operate at a voltage as low as 285 mV while still demonstrating high resilience to process variation. Its noise margin has been elevate