A 0.77 ps RMS Jitter 6-GHz Spread-Spectrum Clock Generator Using a Compensated Phase-Rotating Technique

Abstract

This study demonstrates a 6-GHz triangular-mod- ulated spread-spectrum clock generator (SSCG) based on a fractional- PLL in a 90-nm CMOS process. This paper presents a phase-rotating technique to create the fractional- topology for the SSCG and implement spread-spectrum clocking (SSC) by modulating the fractional- ratios. The proposed phase-rotating technique consists of virtual mult iphase generation and the phase compensation approach. This tec hnique effectively compensates the instantaneous timing error and shows the ignorable quanti- zation error. Unlike the delta-s igma technique commonly used for SSCGs, the proposed SSCG rea lizes non-dithered fractional division ratios. In terms of SSC, this approach suppresses the RMS jitter to less than 1 ps, showing a signi ficant improvement in the jitter performance in this work. T he measured power attenuation of electromagnetic interference (EMI) is 16.12 dB, with a deviation of less than 0.5% (5000 ppm). Operating at a 6-GHz clock rate, the measured RMS jitter with and without the down-spreading spectrum are 0.77 and 0.71 ps, res pectively. The chip core area is less than 0.55 0.45 mm and the core power consumption is 2 7 . 7m Wa tas u p p l yo f1 . 0V .