A 130- W, 64-Channel Neural Spike-Sorting DSP Chip V aibhav Karkare, Student Member , IEEE, Sarah Gibson , Student Member , IEEE, and Dejan Markovi ć, Member , IEEE

Abstract

Spike sorting is an important processing ste pi n various neuroscienti fic and clinical studies. Energy-ef ficient spike-sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings . Spike-sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most ex- isting designs either provide only spike de tection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a spike-sorting DSP chip that can perform d etection, alignment, and feature extraction simultaneousl y for 64 channels. Spike-sorting algorithms chosen based on a com plexity–performance analysis were implemented on ASIC using a MAT LAB/Simulink-based architecture design framework. Energy–delay tradeoffs of the de- sign were analyzed to identify the o ptimal degree of interleaving. T h ec h i pw a si m p l e m e n t e dw i t ham odular architecture, and can be con figured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, i mplemented in a 90-nm CMOS process, has a power dissipation of 130 W( p o w e rd e n s i t yo f 30 W/mm ) when processing all 64 channels and provides a data-rate reduction of 91 .25% (11.71 Mb/s to 1.02 Mb/s).