← 返回 JSSC 论文列表JSSC 2011第4期RF & Wireless90nm CMOSNeural Interface
A 130- W 64-Channel Neural Spike-Sorting DSP Chip V aibhav Karkare Student Membe
一款130μW 64通道神经尖峰排序DSP芯片，支持实时多通道无线神经信号处理。
130μW总功耗（64通道全开时功率密度30μW/mm²），数据率降低91.25%（11.71Mb/s→1.02Mb/s）
神经信号处理尖峰排序多通道ASIC低功耗设计实时DSP
▸64通道并行处理架构
▸基于MATLAB/Simulink的ASIC设计框架
▸可配置通道数（16/32/48/64）与动态功耗门控
Abstract
Spike sorting is an important processing ste pi n
various neuroscienti fic and clinical studies. Energy-ef ficient
spike-sorting ASICs are necessary to allow real-time processing
of multi-channel, wireless neural recordings . Spike-sorting ASICs
have to meet stringent power-density constraints and must provide
significant data-rate reduction for wireless transmission. Most ex-
isting designs either provide only spike de tection for multi-channel
processing, or they provide detection and feature ext