← 返回 JSSC 论文列表JSSC 2011第4期Other90nmHigh-Speed LinkEqualizer
A 625 Gbs V oltage-Time Conversion Based Fractionally Spaced Linear Receive Equa
提出基于电压-时间转换的分数间隔线性接收均衡技术，用于高速链路中的联合均衡与相位同步。
90nm CMOS, 1.2V, 6.25Gb/s, 3.6mW/Gb/s, >4bit线性度
分数间隔线性接收均衡高速链路改进符号-符号LMS算法电压-时间转换自动归零
▸改进的符号-符号最小均方（M-SSLMS）自适应算法避免标准SSLMS算法的发散问题
▸采用具有自动归零功能的基于反相器的阈值检测器实现电压-时间转换
▸在90nm CMOS工艺下实现高能效（3.6mW/Gb/s）和大输入动态范围（>4bit线性度）
Abstract
ng, Student Member , IEEE, and Vladimir Stojanovic´, Member , IEEE
Abstract—Fractionally spaced linear receive equalization
(FSE) is shown in this work as an effective method to perform
joint equalization and phase-synchronization in mesochronous
high-speed links. Given an arbitrary receive sampling phase,
a modified sign-sign least mean squares (M-SSLMS) adaptive
algorithm is developed to tune the FSE tap weights to mitigate the
inter-symbol interference (ISI), avoiding the divergence issue in
t