A 90 nm-CMOS, 500 Mbps, 3–5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization Changhui Hu, Student Member , IEEE, Rahul Khanna, Jay Nejedlo, Kangmin Hu , Student Member , IEEE

Abstract

A fully-integrated, 3–5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 n m-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for cloc k/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Tran smitter pre-emphasis equaliza- tion is utilized to mitigate the effect of multipath on bit-error rate (BER). Occupying 2 mm die area, the transceiver achieves a data rate of 500 Mbps, energy ef ficiency of 0.18 nJ/b at 500 Mbps, and a RX raw BER of 10 across a distance of 10 cm at 125 Mbps. In a real multipath environment, BER improves by 2.35x after equalization of the first multipath re flection.