A 90 nm-CMOS 500 Mbps 35 GHz Fully-Integrated IR-UWB Transceiver With Multipath

Abstract

A fully-integrated, 3–5 GHz Impulse-Radio UWB transceiver with on-chip flash ADC is designed in 90 n m-CMOS. A new scheme for receiver phase acquisition is proposed that uses pulse injection-locking to synchronize the receive clock with the transmitted data, eliminating the need for cloc k/data recovery (CDR), requiring only static receiver phase alignment with the transmitted pulses at startup. Tran smitter pre-emphasis equaliza- tion is utilized to mitigate the effect of multipath on bit-error