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JSSC 2011第4期RF & Wireless0.18μmNeural Network Accelerator

A Linear Multi-Mode CMOS Power Ampli fier With Discrete Resizing and Concurrent P

采用离散重配置和并行组合变压器的线性多模CMOS功率放大器设计
0.18μm CMOS, 3.3V, 峰值输出31dBm/PAE34.8%
功率放大器多模CMOS效率优化可重构
▸离散重配置技术结合并行组合变压器提高低功率模式效率
▸基于变容二极管可调谐匹配电路设计
▸并行组合功率单元最小化变压器功率损耗
Abstract
Efficiency degradation effects of power combining transformers with partially disa bled inputs are quantitatively analyzed. To improve ef ficiencies in lower-power modes of a multi-mode class-AB power ampli fier (PA), a discrete resizing technique is introduced in combin ation with a parallel-combining transformer (PCT). The two-stage PA implemented in a 0.18- m CMOS technology also includes var actor-based tunable matching circuits. The design method involves parallel-combining of two power stages