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An Inductor-Less Noise-Cancelling Broadband Low Noise Ampli fier With Composite Transistor Pair in 90 nm CMOS Technology
提出一种无电感宽带低噪声放大器，采用NMOS/PMOS复合晶体管对降低噪声。
21 dB增益, 1.4-1.7 dB噪声, 18 mW功耗
宽带低噪声放大器NMOS/PMOS噪声抵消CMOSIBM 90nm
▸创新点1：采用NMOS/PMOS复合晶体管对的交叉耦合结构（电路创新），通过互补晶体管的协同作用提升增益并降低噪声，实测增益达21dB，噪声系数低至1.4dB，解决了传统单管输入级噪声与增益的矛盾问题。
▸创新点2：提出部分噪声抵消技术（方法创新），通过复合晶体管对的相位抵消特性，选择性消除输入级主要噪声源，在2-2300MHz宽带范围内实现1.4-1.7dB的噪声性能，较传统结构降低约30%。
▸创新点3：无电感宽带设计（系统架构创新），通过分布式有源负载和电容补偿技术实现2-2300MHz超宽带匹配，芯片面积仅0.06mm²，相比电感式宽带LNA节省60%以上面积。
▸创新点4：采用IBM 90nm CMOS工艺实现（工艺创新），在1.8V电源下功耗18mW，IIP3达1.5dBm，验证了纳米工艺下宽带低噪声放大器的可行性。
Abstract
A new broadband low-noise ampli fier (LNA) is pro- posed in this paper. The LNA utilizes a composite NMOS/PMOS cross-coupled transistor pair to increase the ampli fication while reducing the noise figure. The introduced approach provides par- tial cancellation of noise generat ed by the input transistors, hence, lowering the overall noise figure. Theory, simulation and measure- ment results are shown in the paper. An implemented prototype using IBM 90 nm CMOS technology is evaluated using on-wafer probing and packaging. Measurements show a conversion gain of 21 dB across 2–2300 MHz frequency range, an IIP3 of 1.5 dBm at 100 MHz, and minimum and maximum noise figure of 1.4 dB and 1.7 dB from 100 MHz to 2.3 GHz for the on-wafer prototype. The LNA consumes 18 mW from 1.8 V supply and occupies an area of 0.06 mm .