Abstract
This work addresses the device modeling challenges of production-quality, state-of-th e-art, silicon-on-sapphire (SOS) processes. Differences between SOS , silicon-on-insulator (SOI), and bulk CMOS are highlighted, with emphasis on the key dif- ferences in the modeling methodology. For RF and low-power applications, SOS has distinct advantages over SOI, such as reduced parasitics, better linearity, and enhanced electrical iso- lation. Y et little is reported in t he literature about modeling of a commercially viable SOS process. Though originally developed for SOI, it is demonstrated that the BSIMSOI model can adequately represent SOS MOSFET s, in- cluding fully and partially depleted devices. For RF switch appli- cations, and are captured with reasonable accuracy. An additional RF figure of merit, ,i sa l s or e a s o n a b l yw e l lm o d - eled, yielding peak values in the 40–50 GHz range.