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1-Tbytes 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Com
提出基于3D互连和多核配置的1-Tbyte/s 1-Gbit DRAM架构，解决多核系统内存瓶颈。
45nm工艺, 51.6mm²芯片面积, 19.5W功耗, 51.3 Gbyte/s/W能效
DRAM多核流水线TSV3D互连
▸采用多核配置和3D互连技术（TSV）的DRAM架构
▸五级流水线架构减少数据总线操作周期至2ns
▸低噪声早期写入方案和16-Gbit/s I/O电路
Abstract
no, Akira Kotabe, and Y oshimitsu Y anagawa
Abstract—Aiming to resolve memory bottlenecks in multi-core
system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on
a multi-core configuration and 3-D interconnects was devel-
oped. The DRAM stacked on a multi-core CPU has 512-bit I/Os
with through-silicon-via (TSV) distributed in 16 memory cores.
Five-stage pipelined architecture in the compact DRAM core was
developed to reduce the operation cycle of the data-bus to 2 ns. A
low-noise early-bar-write