← 返回 JSSC 论文列表JSSC 2011第5期Wireline I/O45nmProcessor/CPU
53 Gbps Native /71/70/40/50/52/41/50Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors Sanu K. Mathew , Member , IEEE
45nm CMOS工艺下的高性能AES加密解密硬件加速器，实现53 Gbps的AES-128性能
53/44/38 Gbps AES-128/192/256性能, 125 mW, 1.1 V, 50°C
AES加密硬件加速器复合域算术低功耗设计高性能计算
▸创新点1：原生复合域算术计算（方法创新） - 采用100%原生复合域算术计算，优化了Sbox的延迟和面积，实现了37%的Sbox延迟减少和25%的面积缩减，同时提升了整体加密效率。
▸创新点2：可重构加密解密数据路径（系统创新） - 设计了统一的可重构数据路径，支持加密和解密操作，显著提高了硬件的灵活性和效率，同时减少了电路复杂度。
▸创新点3：优化的复合域多项式（方法创新） - 通过优化复合域多项式，提升了算术运算的效率，减少了计算延迟，从而实现了更高的吞吐量（53/44/38 Gbps AES-128/192/256）。
▸创新点4：折叠式ShiftRow数据路径（电路创新） - 采用折叠式ShiftRow数据路径设计，减少了67%的最坏情况互连长度和33%的ShiftRow布线轨道，显著降低了布线复杂度和面积占用。
Abstract
This paper describes an on-die, reconfigurable AES encrypt/decrypt hardware accelerator fabricated in 45 nm CMOS, targeted for content-protection in high-performance microproces- sors. 100% round computation in native /71/70/40/50/52/41/50composite-field arithmetic, unified reconfigurable datapath for encrypt/decrypt, optimized ground & composite-field polynomials, integrated affine/bypass multiplexer circuits, fused Mix/InvMixColumn cir- cuits and a folded ShiftRow datapath enable peak 2.2 Tbps/Watt AES-128 energy efficiency with a dense 2-round layout occupying 0.052 mm /50, while achieving: (i) 53/44/38 Gbps AES-128/192/256 performance, 125 mW, measured at 1.1 V , 50 C, (ii) scalable AES-128 performance up to 66 Gbps, measured at 1.35 V , 50 C, (iii) wide operating supply voltage range with robust subthreshold voltage performance of 800 Mbps, 409 W, measured at 320 mV , 50 C (iv) 37% Sbox delay reduction and 25% area reduction with a compact Sbox layout occupying 759 m/50(v) 67% reduction in worst-case interconnect length and 33% reduction in ShiftRow wiring tracks and (vi) 43% reduction in Mix/InvMixColumn area with no performance penalty.