JSSC 2011第5期RF & Wireless130nmTransceiverDRAM

A 250 mV 352 22W GPS Receiver RF Front-End in 130 nm CMOS

提出了一种250mV供电的GPS接收机射频前端，功耗仅为352μW，创下最低记录。

250mV, 352μW, 42dB增益, 7.2dB噪声系数, -112.4dBc/Hz相位噪声

GPS接收机射频前端超低电压CMOS功耗优化

▸创新点1：亚阈值偏置技术 - 通过系统性地优化电路在超低电压下的工作状态，采用亚阈值偏置技术显著降低了供电电压至250 mV，这是迄今为止集成接收器RF前端中最低的供电电压，实现了3倍的功耗节省。

▸创新点2：新型混频器-VCO接口 - 提出了一种创新的混频器与压控振荡器（VCO）接口设计，优化了信号传输效率，降低了相位噪声，实测相位噪声为112.4 dBc/Hz @ 1 MHz偏移，VCO FoM达到187.4 dBc/Hz。

▸创新点3：电荷中和技术 - 通过电荷中和技术的应用，有效减少了电路中的寄生效应，提升了整体系统的线性度和噪声性能，噪声系数低至7.2 dB，系统增益高达42 dB。

▸创新点4：全集成低功耗设计 - 在130 nm CMOS工艺中实现了全集成GPS接收器RF前端，包含可变增益LNA、正交VCO、正交混频器及所需偏置电路，总功耗仅为352 µW，为同类产品中最低功耗之一。

Abstract

A fully integrated CMOS GPS receiver RF front-end is presented. Systematic circuit optimizations for ultra-low voltage operation including subthreshold biasing, a novel mixer-VCO in- terface, and charge neutralization enable the supply voltage to be dramatically reduced as a means to save power. The 250 mV supply is the lowest ever reported for any integrated receiver RF front-end to date. Its 352 W power consumption represents a three times power savings compared to the prior lowest GPS receive