← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2011第5期Wireline I/O40nm

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode

开发了一种5Gb/s源同步信号系统,采用新的时钟/数据偏差最小化技术,提高了高频传输抖动容忍度。
5Gb/s, TSMC 40nm LP CMOS
共模时钟嵌入式时钟集成采样器低功耗匹配源同步
使用发射时钟延迟线和集成接收器减少时钟/数据偏差
通过共模时钟嵌入减少时钟分布延迟
支持快速启动,无需传统源同步系统的时钟缓冲延迟
Abstract
Member , IEEE, Lei Luo , Member , IEEE, William Stonecypher, Member , IEEE, Wayne Dettloff , Senior Member , IEEE, John C. Eble , Member , IEEE, Teva Stone, Jihong Ren , Member , IEEE, Brian Leibowitz , Member , IEEE, Michael Bucher , Member , IEEE, Patrick Satarzadeh, Member , IEEE, Qi Lin, Y ue Lu, and Ravi Kollipara , Senior Member , IEEE Abstract—A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization tech- nique. The method incorporates a tra