7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS

Abstract

A high-frequency jitter tolerant receiver in 65 nm CMOS is presented. Jitter toleran ce is improved by tracking cor- related jitter using a pulsed clock forwarded from the transmitter side. The clock receiver comprise s two injection locked oscilla- tors to frequency-multiply, des kew, and adjust jitter tracking bandwidth. Different data rates and latency mismatch between the clock and data paths are accommodated by a jitter tracking bandwidth that is controllable up to 300 MHz. Each receiver con- sumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz.