A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle

Abstract

This paper presents an area ef ficient 10-bit, 40 MS/s SAR ADC. The design strategy to minimize the circuit area adopts the pipelined architecture. The 10-bit SAR ADC is divided into 4-bit (first stage) and 6-bit (second stage) SAR ADC. The two-stage pipelined structure achieves a reduction of the number of capaci- t o r s ,w h i c hi st h ed o m i n a n ts o u r c eo ft h ec i r c u i ta r e ao fS A RA D C s . To avoid the comparator offset issu e, the proposed single-ended 1.5 bit/cycle algorithm is used in the first stage. The single-ended scheme reduces the conversion cycle while maintaining suf ficient tolerance of the comparator offs et. The second stage uses a pseudo C-2C architecture that is useful for minimizing the load capac- itance of the residue ampli fier and minimizing the circuit area. Fabricated in 65-nm CMOS with an active area of 0.06 mm ,i t achieves a peak SNDR of 55.1 dB and a peak SFDR of 71.5 dB at 40 MS/s sampling rate. The power consumption is 1.21 mW.