← 返回 JSSC 论文列表JSSC 2011第6期Data Converters65nmSAR ADC
A 10-bit 40-MSs 121 mW Pipelined SAR ADC Using Single-Ended 15-bitcycle Conversi
本文提出了一种面积高效的10位40MS/s流水线SAR ADC，采用单端1.5位/周期转换算法以减少比较器偏移影响。
10-bit, 40 MS/s, 55.1 dB SNDR, 71.5 dB SFDR, 1.21 mW
SAR ADC流水线架构单端转换C-2C架构低功耗
▸采用流水线架构减少电路面积
▸单端1.5位/周期转换算法避免比较器偏移问题
▸第二级采用伪C-2C架构减少残留放大器负载电容
Abstract
This paper presents an area ef ficient 10-bit, 40 MS/s
SAR ADC. The design strategy to minimize the circuit area adopts
the pipelined architecture. The 10-bit SAR ADC is divided into
4-bit (first stage) and 6-bit (second stage) SAR ADC. The two-stage
pipelined structure achieves a reduction of the number of capaci-
t o r s ,w h i c hi st h ed o m i n a n ts o u r c eo ft h ec i r c u i ta r e ao fS A RA D C s .
To avoid the comparator offset issu e, the proposed single-ended
1.5 bit/cycle algorith