A 3T Gain Cell Embedded DRAM Utilizing Preferential Boosting for High Density and Low Power On-Die Caches Ki Chul Chun, Pulkit Jain, Jung Hwa Lee, and Chris H. Kim , Senior Member , IEEE

Abstract

Circuit techniques for enabling a sub-0.9 V logic-com- patible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell utilizes Read Word-line (RWL) preferential boosting to increase read margin and improve data retention time. Read speed is enhanced with a hybrid current/voltage sense ampli fier that al- lows the Read Bit-line (RBL) to remain close to VDD. A regu- lated bit-line write scheme for driving the Write Bit-line (WBL) is equipped with a steady-state storage node voltage monitor to over- come the data ‘1’ write disturbance problem of the PMOS gain cell without introducing another boosted supply for the Write Word- line (WWL) over-drive. An adaptive and die-to-die adjustable read reference bias generator is proposed to cope with PVT variations. Monte Carlo simulations compare the 6-sigma read and write per- formance of proposed eDRAM against conventional designs. Mea- surement results from a 64 kb eDRAM test chip implemented in a 65 nm low-leakage CMOS process show a 1.25 ms data retention time with a 2 ns random cycle time at 0.9 V , 85 C, and a 91.3 W per Mb static power dissipation at 1.0 V , 85 C.