← 返回 JSSC 论文列表JSSC 2011第7期RF & Wireless90nmSAR ADC
A2 6 W 8 bit 10 MSs Asynchronous SAR ADC for Low Energy Radios
一款用于低能耗无线电的6nW待机功耗、8位10MS/s异步SAR ADC
90nm CMOS, 1V, 10.24MS/s, 7.77bit ENOB, 12fJ/step
异步SAR ADC低功耗动态逻辑电容定制能量效率
▸电路创新：采用0.5 fF定制单元电容，显著降低模拟功耗，优化了电容阵列的尺寸和匹配精度，提升了ADC的整体能效。
▸电路创新：引入异步动态逻辑设计，有效降低数字电路的功耗，同时提高了转换速度，特别适用于低功耗无线通信系统。
▸方法创新：开发专用CAD工具评估定制电容的工艺变异，确保电容阵列的稳定性和一致性，提高了设计的可靠性和可制造性。
▸系统创新：全动态设计优化低泄漏电流，实现6 nW的待机功耗，使得ADC在极低采样率下仍能保持高能效，适用于间歇性工作的低功耗设备。
Abstract
This paper presents an asynchronous SAR ADC for
flexible, low energy radios. To achieve excellent power ef ficiency
for a relatively moderate resolution, various techniques are in-
troduced to reduce the power consumption: custom-designed
0.5 fF unit capacitors minimize the analog power consumption
while asynchronous dynamic logic minimizes the digital power
consumption. The variability of the custom-designed capacitors
is estimated by a specialized CAD tool and veri fied by chip mea-
surements. An