JSSC 2011第7期Data Converters65nmPipeline ADC

A 24 GSs Single-Channel 313 dB SNDR at Nyquist Pipeline ADC in 65 nm CMOS

本文介绍了一种采用65nm CMOS工艺的2.4 GS/s高速单通道流水线ADC。

65nm CMOS, 2.4 GS/s, 31.3 dB SNDR@Nyquist

高速ADC流水线结构开环放大器电流模式多GS/s

▸创新点1：快速开环电流模式放大器（电路创新）：采用开环电流模式放大器，显著提升放大器的速度，支持2.4 GS/s的高采样率，解决了传统闭环放大器在高频下的速度限制问题。

▸创新点2：早期比较方案（方法创新）：通过优化子ADC的采样时序，提前进行比较操作，减少信号处理延迟，确保在高速采样下的信号完整性和准确性。

▸创新点3：多GS/s流水线ADC可行性验证（系统创新）：在65 nm CMOS工艺下实现单通道2.4 GS/s的流水线ADC，SNDR在Nyquist频带内超过30.1 dB，验证了多GS/s流水线ADC在交织结构中的可行性。

▸创新点4：子ADC采样实例边界分析（方法创新）：基于充分稳定性和亚稳态分析，优化子ADC的采样实例，确保在高采样率下的决策准确性，提升整体ADC的可靠性。

Abstract

This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample rate is achieved through the use of fast open-loop current-mode ampli ﬁers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufﬁcient settling for a decision as well as metastability. Imple- mented in a 65 nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency