← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2011第7期RF & Wireless90nmSAR ADCNeural Network Accelerator

A Fully-Integrated, Short-Range, Low Data Rate FM-UWB Transmitter in 90 nm CMOS Nitz Saputra and John R. Long , Member , IEEE

本文介绍了一种90纳米CMOS工艺下实现的3-5 GHz频段全集成FM-UWB发射机。
900 μW功耗,9 nJ/bit能效,100 kbits/s数据传输率
FM-UWBCMOS发射机频率校准能效优化
全集成FM-UWB发射机设计
采用SAR算法和全数字FLL进行频率校准
片上集成所有电压和电流参考
Abstract
This paper presents a fully-integrated 3–5 GHz-band FM-UWB transmitter implemented in 90 nm bulk CMOS. The front-end consists of an RF current-controlled oscillator (RF-ICO) and class-AB power amplifier. Transmit data modulates a sub-car- rier oscillator. The 2-FSK modulated output is ampli fied by a transconductor, and directly modulates the RF-ICO tune input. A successive approximation register (SAR) algorithm and on-chip all-digital frequency-locked loop (FLL) calibrate the carrier and sub-carrier frequencies. All voltage and current references required by the transmitter are included on-chip. The 0.2 0.5 mm active area transmitter consumes 900 Wf r o ma1V supply. Energy ef ficiency of the transmitter is 9 nJ/bit running continuously at 100 kbits/s.