← 返回 JSSC 论文列表JSSC 2011第7期Clocking & PLLs0.5 μm CMOSNeural Network Accelerator
A Low-Power High-PSRR Clock-Free Current-Controlled Class-D Audio Ampli fier Joselyn Torres, Student Member , IEEE , Adrian Colli-Menchi , Student Member , IEEE
提出一种低功耗、高PSRR、无时钟的电流控制D类音频放大器,采用积分滑模控制实现稳健操作和最小稳态误差。
82 dB PSRR, >90 dB SNR, 0.02% THD+N, 90 dBc PS-IMD, 410 mW输出功率, 84%峰值效率
D类放大器积分滑模控制高PSRR低功耗音频放大器
▸创新点1:积分滑模控制(ISMC)方法创新。采用积分滑模控制技术,显著提升了系统的鲁棒性,并有效减少了稳态误差,确保音频信号的高保真输出。
▸创新点2:双反馈环路设计(电压环和电流环)系统创新。通过外环电压反馈和内环电流反馈的协同工作,精确跟踪输入信号,实现了高达82 dB的电源抑制比(PSRR)和超过90 dB的信噪比(SNR)。
▸创新点3:低功耗控制器设计电路创新。优化控制器电路,使其功耗比近期发表的作品减少30%,在2.7 V单电源供电下实现了84%的峰值效率,最大输出功率达410 mW。
▸创新点4:无时钟设计系统创新。采用无时钟架构,避免了传统时钟信号引入的噪声和失真,进一步提升了音频放大器的整体性能,总谐波失真加噪声(THD+N)低至0.02%。
Abstract
A low power, high PSRR, clock-free, current-con- trolled class-D audio power ampli fier is presented. The proposed audio amplifier utilizes integral sliding mode control (ISMC) to en- sure robust operation and to minimize the steady-state error. This architecture has two feedback loops: an outer voltage loop that minimizes the voltage error between the input and output audio signals, and an inner current loop that measures the inductor cur- rent to track the input signal accurately. The proposed ampli fier achieves up to 82 dB of power supply rejection ratio (PSRR), more than 90 dB of signal-to-noise (SNR) ratio over the entire audio band, and total harmonic distortion plus noise (THD+N) as low as 0.02%. A power-supply-induced intermodulation distortion (PS-IMD) of approximately 90 dBc was measured for an input voltage signal of 2 at 1 kHz and a sinusoidal power-supply ripple of 300 mV at 217 Hz superimposed on the DC level. The IC prototype’s controller consumes 30% less power than those of recently published works. The audio ampli fier operates with a 2.7-V single voltage supply and d elivers a maximum output power of 410 mW with 84% peak ef ficiency ( )i n t oa n8 speaker. It was fabricated using 0.5 m CMOS standard technology, and occupies a total active area of 1.65 mm .