A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking Wenjing Yin, Student Member , IEEE, Rajesh Inti , Student Member , IEEE,A m r E lshazly, Student Member , IEEE, Brian Y oung, Student Member , IEEE, and Pavan

Abstract

A digital phase-locked loop (DPLL) employs a linear proportional path, a double inte gral path, bandwidth and tuning range tracking; and a novel delta-sigma digital to analog converter to achieve low jitter , wide operating range and low power. The pro- posed proportional path decouples the detector quantization error and oscillator noise bandwidth tradeoff and helps maximize band- width to suppress digitally controlled oscillator (DCO) phase noise in a power ef ficient manner. A double integral path alleviates the tradeoff between DCO tuning range and its frequency quantization error. The high resolution of the DCO was maintained over a wide range of sampling clock frequencie sb yu s i n gad e l t a - s i g m ad i g i t a l to analog converter and a continuously tunable switched-RC filter. Bandwidth and tuning range tracking are employed to achieve low jitter over the entire operating r ange. The prototype DPLL, fabri- cated in a 90 nm CMOS process, operates from 0.7 GHz to 3.5 GHz. At 2.5 GHz, the proposed DPLL consumes only 1.6 mW power from a 1 V supply and achieves 1.6 ps and 11.6 ps of long-term r.m.s and peak jitter, respectively.