← 返回 JSSC 论文列表JSSC 2011第8期Data Converters90 nm CMOSDelta-Sigma ADCPLL
A 07-to-35 GHz 06-to-28 mW Highly Digital Phase-Locked Loop With Bandwidth Track
一种采用线性比例路径和双积分路径的数字锁相环，实现低抖动、宽操作范围和低功耗。
0.7 GHz至3.5 GHz操作范围，2.5 GHz时功耗1.6 mW，长期r.m.s抖动1.6 ps，峰值抖动11.6 ps
数字锁相环低功耗低抖动宽操作范围delta-sigma数模转换器
▸线性比例路径解耦检测器量化误差和振荡器噪声带宽权衡
▸双积分路径缓解DCO调谐范围与其频率量化误差的权衡
▸采用delta-sigma数模转换器和可调谐RC滤波器维持高分辨率
Abstract
A digital phase-locked loop (DPLL) employs a linear
proportional path, a double inte gral path, bandwidth and tuning
range tracking; and a novel delta-sigma digital to analog converter
to achieve low jitter , wide operating range and low power. The pro-
posed proportional path decouples the detector quantization error
and oscillator noise bandwidth tradeoff and helps maximize band-
width to suppress digitally controlled oscillator (DCO) phase noise
in a power ef ficient manner. A double integral