← 返回 JSSC 论文列表JSSC 2011第8期Data Converters0.13μmSAR ADCDAC
A 550-22W 10-b 40-MSs SAR ADC With Multistep Addition-Only Digital Error Correct
提出了一种采用多步仅加法数字误差校正的10位异步SAR ADC，提升了转换速度。
CMOS 0.13μm, 1.2V, 40MS/s
SAR ADC数字误差校正异步多步二进制校正电容DAC
▸创新点1：多步仅加法数字误差校正（ADEC）是一种方法创新，通过多步冗余决策周期实现误差校正，仅使用加法运算简化了数字校正逻辑，显著降低了硬件开销和功耗，同时保证了10位线性度。
▸创新点2：简化的DAC切换算法是一种电路创新，通过优化DAC切换顺序和逻辑，减少了电容切换的复杂度和能量消耗，提升了转换速度37%，同时保持了高精度。
▸创新点3：虚拟分割电容DAC是一种系统创新，将电容DAC分为三个子DAC以实现误差校正，无需额外硬件，显著降低了面积和功耗，同时提高了系统的灵活性和可靠性。
▸创新点4：异步SAR ADC设计是一种电路创新，通过异步时钟控制逻辑优化了转换时序，实现了50.6-dB SNDR和50 fJ/conversion-step的优异性能指标，适用于高速低功耗应用。
Abstract
g-Kyo Lee , Student Member , IEEE, Jong-Kee Kwon , Member , IEEE,
and Seung-Tak Ryu , Member , IEEE
Abstract—A speed-enhanced 10-b asynchronous SAR ADC
with multistep addition-only digital error correction (ADEC) is
presented with a straightforward DAC switching algorithm. The
capacitor DAC is virtually divided into three sub-DACs for ADEC
with negligible hardware overhead. The redundant decision cycles
between stages reconfigure the capacitor connection of the DAC.
These redundancies guarantee 1