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JSSC 2011第8期RF & Wireless65nm

CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated

探讨CMOS技术缩放对多Gbps光接收器的影响及新机遇
65nm CMOS, 10+ Gbps
CMOS技术缩放光接收器深n阱响应度均衡技术
利用缩放技术提升TIA性能以改善光检测器带宽
采用深n阱的光晶体管结构显著提高响应度
均衡技术在CMOS集成光检测器中的应用潜力
Abstract
The integration of photodetectors for optical com- munication into standard nanoscale CMOS process technologies can enable low cost for emerging high volume short-reach parallel optical communication. Whereas past work has highlighted the challenges that face integrated photodetectors in highly sca led CMOS technologies, this work e xamines the opportunities af- forded by these new technologies. First, scaling promises improved extrinsic photodetector bandwidth thanks to improved TIA p er- formance. Second, modern advanced process features enable new photodetector structures with improved performance. A phototransistor employing deep n-wells is charact erized in 65-nm CMOS and exhibits a more than ten-fold increase in responsivity over a similar structure without t he buried n-well. Third, equal- ization techniques bene fit from technology scali ng and are only just beginning to be applied to CMOS integrated photodetectors. In particular, decision feedback equalization appears to offer potential for 10+ Gbps operation.