Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs Gokce K

Abstract

Process variations in advanced CMOS nodes limit the benefits of scaling for analog designs. I nt h ep r e s e n c eo fi n c r e a s i n g random intra-die variations, mismatch becomes a signi ficant de- sign challenge for circuits such ascomparators. In this paper we de- scribe and demonstrate the details of a statistical element selection (SES) methodology that relies on the combinatorial growth of sub- sets of selectable circuit elements (e.g., input transistors in a com- parator) to provide red