Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs

Abstract

Process variations in advanced CMOS nodes limit the benefits of scaling for analog designs. I nt h ep r e s e n c eo fi n c r e a s i n g random intra-die variations, mismatch becomes a signi ficant de- sign challenge for circuits such ascomparators. In this paper we de- scribe and demonstrate the details of a statistical element selection (SES) methodology that relies on the combinatorial growth of sub- sets of selectable circuit elements (e.g., input transistors in a com- parator) to provide redundancy for post-manufacturing calibra- tion of specifications (e.g., offset). A test chip consisting of an array of digitally calibrated comparators with built-in combinatorial re- dundancy was manufactured in 65 nm bulk CMOS. Over 99.5% of the comparators satisfy the given offset speci fication compared to 15% for Pelgrom-type sizing. A second test chip in the same process consists of an 8-bit, 1.5 GS/s flash ADC and achieves 37 db SNDR at low frequencies. The total power is 35 mW, 20 mW in the S&H a n d1 5m Wi nt h eA D Cc o r e .T h efigure of merit is 0.42 pJ/conv.