← 返回 JSSC 论文列表JSSC 2011第8期RF & Wireless90nmEqualizer
Fully Digital Transmit Equalizer With Dynamic Impedance Modulation Ranko Sredojević, Student Member , IEEE, and Vladimir Stojanovi ć,M e m b e r ,IEEE
该论文提出了一种全数字传输均衡器,采用动态阻抗调制技术,实现了高能效的信号传输。
4 Gb/s, 2 pJ/bit, 100 mV接收眼图
数字均衡器动态阻抗调制能效预加重CMOS
▸创新点1:动态阻抗调制技术(电路创新):通过动态调整驱动器的输出阻抗,显著提升了能量效率,相比传统的阻抗恒定电流和电压模式驱动器,在4 Gb/s速率下实现了2 pJ/bit的能量效率。
▸创新点2:全数字RAM-DAC后端(系统创新):采用全数字RAM-DAC后端进行模式查找,有效补偿了占空比失真和驱动器非线性,同时提供了可编程的预加重功能,增强了系统的灵活性和性能。
▸创新点3:可编程预加重(方法创新):通过可编程预加重机制,能够根据不同的背板条件动态调整信号预加重,优化信号传输质量,适应多种20英寸背板环境。
▸创新点4:90-nm CMOS工艺实现(电路创新):在90-nm CMOS工艺下成功实现该技术,展示了其在先进工艺节点下的可行性和高效性,为未来更高集成度的设计提供了参考。
Abstract
This paper analyzes the energy ef ficiency of different transmit equalizer driver topol ogies. Dynamic impedance mod- ulation is found to be the most energy-ef ficient mechanism for transmit pre-emphasis, when c ompared with impedance-main- taining current and voltage-mode drivers. The equalizing transmitter is implemented as a digital push–pull impedance-modulating (RM) driver with fully digital RAM-DAC back-end for pattern lookup. Thi s back-end compensates for both duty-cycle distortion and drive r nonlinearity, while providing a programmable pre-emphasis. A testchip fabricated in 90-nm CMOS process shows relatively small signal degradation from dynamic modulation of driver output impedance over a variety of 20 backplanes at 4 Gb/s, with energy ef ficiency of 2 pJ/bit at 100 mV of receiver eye. Despite this signal degradation, at the same performance point, the impedance modulating driver shows better energy ef ficiency than impedance-ma intaining current and voltage-mode drivers.