← 返回 JSSC 论文列表JSSC 2011第8期Data Converters90nm CMOSPipeline ADC
SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration Pingli Hua
一种无专用前端采样保持放大器的10位100MS/s流水线ADC，采用背景时钟偏移校准技术。
10位, 100MS/s, 12.2mW, 0.26mm², 71dB SFDR, 55dB SNDR
流水线ADC时钟偏移校准背景校准梯度下降算法无采样保持放大器
▸无专用前端采样保持放大器（SHA-less）设计
▸采用原位背景时钟偏移校准技术
▸使用梯度下降算法自适应调整前端子ADC时序
Abstract
r Lu, Peiyuan Wan,
Seung-Chul Lee, Student Member , IEEE, Wenbo Liu , Member , IEEE, Bo-Wei Chen , Student Member , IEEE,
Y ung-Pin Lee, Wen-Tsao Chen, Tzu-Yi Y ang, Gin-Kou Ma, and Y un Chiu , Senior Member , IEEE
Abstract—A 10-b, 100-MS/s pipelined analog-to-digital con-
verter (ADC) without dedicated front-end sample-and-hold
amplifier (SHA) converts from dc to the 12th Nyquist band
with in situ , mostly digital background calibration for the clock
skew in the 3.5-b front-end stage. The skew i