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A 08 ps DNL Time-to-Digital Converter With 250 MHz Event Rate in 65 nm CMOS for
提出一种65nm CMOS工艺下的08 ps DNL时间数字转换器，适用于250 MHz事件率。
65nm CMOS, 250 MHz event rate, 5.66 mW, 0.006 mm²
时间数字转换器脉冲宽度调制时间模式65nm CMOS动态范围
▸时间模式TDC替代传统电压模式ADC的多位量化器和反馈DAC
▸脉冲宽度调制器将采样电压转换为数字脉冲
▸时间量化反馈脉冲模拟传统ADC中的电压DAC
Abstract
A time-to-digital converter (TDC) is proposed to re-
place the multi-bit quantizer and the multi-bit feedback DAC of
traditional voltage-mode
modulator. Since time-mode systems
process analog signals encoded in the time dimension rather than
the voltage dimension, the proposed time-mode TDC makes the
multi-bit
ADC digital friendly and more suitable for nano-
metric technologies. A pulse-width-modulator (PWM) converts the
sampled-and-held voltage-sampl e to a digital pulse whose width is
proporti