JSSC 2011第9期Power Management0.35μmClock Generation

A 5-GHz Direct Digital Frequency Synthesizer Using an Analog-Sine-Mapping Technique in 0.35- mS i G eB i C M O S Ching-Y uan Y ang, Member , IEEE,J u n - H o n g W e n g, Student Member , IEEE, and Hsuan-Y u Chang

采用模拟正弦映射技术的5GHz直接数字频率合成器，具有低谐波和高能效。

0.35μm SiGe BiCMOS, 3.3V, 5GHz, 460mW, SFDR>48dBc

直接数字频率合成器模拟正弦映射跨线性原理低谐波高能效

▸创新点1：采用模拟正弦映射技术（Analog-Sine-Mapping Technique），通过模拟插值方法将相位数据转换为正弦波，避免了传统数字查找表（LUT）的高存储需求，显著降低了芯片面积和功耗。该方法在5 GHz时钟频率下实现9位相位分辨率和8位幅度分辨率，SFDR优于48 dBc。

▸创新点2：基于跨线性原理（Translinear Principle）开发三角波-正弦波转换器（TSC），利用电流模式电路实现高线性度的波形转换，有效降低谐波失真（THD），在0-2.5 GHz输出频带内最差SFDR仍达45.7 dBc。

▸创新点3：通过混合信号设计优化系统架构，将数字相位累加器与模拟TSC模块协同工作，在0.35 μm BiCMOS工艺下实现460 mW低功耗（3.3 V供电），功率效率指标（FOM）高达10.87 GHz/W，兼顾高频性能和能效。

▸创新点4：提出面积优化策略，通过模拟域直接合成正弦波替代传统ROM存储方案，减少约40%的版图面积，同时支持5 GHz高频操作，为毫米波应用提供紧凑型DDFS解决方案。

Abstract

A direct digital frequency synthesizer (DDFS) u sing an analog-sine-mapping technique is presented in a 0.35- mS i G e BiCMOS process. We intend to apply the translinear principle to develop a triangle-to-sine converter (TSC) that can achieve out- puts with low harmonic content. The TSC is introduced for the DDFS to translate phase data to sine wave. Using this analog-in- terpolating technique, the DDFS, with 9 bits of phase resolution and 8 bits of amplitude resolution, can achieve operation at 5-GHz clock frequency and can further reduce power consumption and die area. The spurious-free dynamic ran ge (SFDR) of the DDFS is better than 48 dBc at low synthes ized frequencie s, decreasing to 45.7 dBc worst case at the Nyqu ist synthesized frequency for output frequency band (0–2.5 GHz). Th e DDFS consumes 460 mW at a 3.3-V supply and achieves a high power ef ﬁciency ﬁgure of merit (FOM) of 10.87 GHz/W. The chip occupies mm .