A Programmable Vision Chip Based on Multiple Levels of Parallel Processors Wancheng Zhang

Abstract

This paper proposes a novel programmable vision chip based on multiple levels of parallel processors. The chip integrates CMOS image sensor, multiple-levels of SIMD parallel p r o c e s s o r sa n da ne m b e d d e dm i c r o p r o c e s s o ru n i t( M P U ) .T h e multiple-levels of SIMD paralle l processors consist of an array processor of SIMD processing elements (PEs) and a column of SIMD row processors (RPs). The PE array and RPs hav ea n parallelism and an parallelism, respectively. The PE array and RPs can be recon figured to handle algorithms with different complexities and processing sp eeds. The PE array, RPs and MPU can execute low-, mid- and high-level image processing algorithms, respectively, which ef ficiently increases the performance of the vision chip. The v ision chip can satisfy flexibly the needs of different vision applications such as image pre-processing, complicated feature extraction and over 1000 fps high-speed image capture. A prototyp ec h i pw i t h1 2 8 28 image sensor, 128 A/D convert ers, 32 8-bit RPs and 32 128 PEs is fab- ricated using the 0.18 CMOS process. Applications including target tracking, pattern extracti on and image recognition are demonstrated.