A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface Hyung-Joon Chi, Jae-Seung Lee, Seong- Hwan Jeon, Seung-Jun Bae, Y oung-Soo Sohn

Abstract

A 3.8 Gb/s multi-drop sing le-ended integrating DFE (IDFE) receiver is implemented in a 0.18 um CMOS by using a single-loop LMS-algorithm to find the DFE coef ficients automat i- cally. Initially, a preamble input data pattern (’1101’) is applied to the main IDFE circuit to determine the DFE coef ficients, while a fixed input data pattern (’1111’) is applied to the replica ID FE cir- cuit. The difference between the outputs of the two IDFE circuits is used in the feedback loop to determine the DFE coef ficients. The reference voltage (Vref) of preamplifier is generated inside chip by a Vref loop to reduce the effect of the external noise and the input offset voltage of preampli fier and IDFE circuits and also to track the mid-level of the input data swing in spite of pr ocess variations of TX chips. An integrating deskew scheme with a minimum over- head is introduced. 2-drop and 4-drop DRAM channels are tested. The maximum data rate was increased from 1.0 Gb/ st o2 . 6G b / s by DFE in the heavily loaded 4-drop interface, from 3.5 Gb/s to 3.8 Gb/s by DFE in the 2-drop interface.