JSSC 2011第9期Other65nm

Crosstalk-Aware PWM-Based On-Chip Links With Self-Calibration in 65 nm CMOS

本文提出两种基于PWM的串扰感知信号技术，用于高效能片上全局总线。

65nm CMOS, 5mm on-chip links, 15%性能提升, 46%峰值能耗降低, 25%平均能耗降低, 2X漏电降低

PWM串扰感知自校准片上总线能耗优化

▸创新点1：基于PWM的串扰感知信号技术（方法创新）。通过将两位信息编码为跃迁类型和脉冲宽度，实现在单根线上的高效传输，相比传统中继器方案提升15%性能并降低46%峰值能耗。

▸创新点2：预校正技术补偿串扰影响（电路创新）。针对脉冲信号受串扰的失真问题，提出预校正电路主动补偿相邻线路耦合效应，使平均能耗降低25%。

▸创新点3：自校准电路减少工艺变化影响（系统创新）。集成片上校准模块动态调整编解码器参数，在65nm工艺下将21个芯片的延迟差异缩小2.5倍，显著提升良率。

▸创新点4：双模式能量优化架构（系统创新）。结合脉冲宽度调制与串扰抑制技术，实现2倍漏电功耗降低，适用于长距离全局总线场景。

Abstract

This paper proposes two crosstalk-aware sig- naling techniques based on pulse width modulation (PWM) for energy-efﬁcient on-chip global busses. Two bits of information are encoded into transition type and pulse width for transmission over one wire. The effect of crosstalk on pulses is compensated by pre-correction techniques and self-calibration circuitry mitigates variability. Measurements from 5 mm on-chip links in 65 nm CMOS show that the proposed schemes simultaneously achieve 15% performanc