← 返回 JSSC 论文列表JSSC 2011第9期RF & Wireless0.13-μm SiGe BiCMOSClock Generation
Frequency-Hopped Quadrature Frequency Synthesizer in 0.13- m Technology Narasimha R. Lanka , Student Member , IEEE , Satwik A. Patnaik , Member , IEEE,a n d
本文提出了一种基于次谐波注入锁定的快速跳频正交频率合成器架构,适用于Wireless-USB/WiMedia标准。
锁定时间小于2.5 ns,相位噪声114 dBc/Hz@1 MHz偏移,正交精度优于0.5度,功耗14.5 mW
频率合成器正交输出快速跳频次谐波注入锁定CMOS
▸创新点1:基于次谐波注入锁定的正交数字控制振荡器(方法创新)。该技术通过次谐波注入锁定实现高精度正交输出,相位噪声低至114 dBc/Hz @1MHz偏移,相比传统LC振荡器显著提升了相位噪声性能和频率稳定性。
▸创新点2:快速频率跳频技术(系统创新)。采用动态闭环控制架构实现2.5ns超快跳频时间,支持Wireless-USB/WiMedia标准,较现有方案提速3倍以上,同时保持47dB最佳杂散抑制。
▸创新点3:纯CMOS工艺实现(电路创新)。在0.13μm SiGe BiCMOS工艺中仅使用CMOS器件完成设计,面积仅0.27mm²,功耗14.5mW,创下同类合成器最低功耗纪录。
▸创新点4:片上集成正交精度测试结构(测试创新)。内置混频器直接测量输出正交精度(<0.5°误差),无需外部仪器介入,为高频系统提供可测性设计范例。
Abstract
This paper presents a Wireless-USB/WiMedia-com- pliant fast-hopping frequency s ynthesizer architecture with quadrature outputs based on sub-ha rmonic injection-locking. The synthesizer features a cross-coup led quadrature digitally-con- trolled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamic s of the quadrature injection-loc ked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only imple- mentation and has been fabricated in a 0.13- m SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement resu lts indicate lock-times of less than 2.5 ns, a locked phase noise of 114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5 . The frequency synthesizer (excluding output buffe rs) occupies an area of 0.27 mm and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopp ing quadrature frequency synthesizer that has been reported to date.