JSSC 2011第10期Power Management0.18μmSRAMDRAM

A0 5VO p e r a t i o n Loss Compensated DRAM Word-Line Booster Circuit for Ultr

提出一种0.5V低功耗高速DRAM字线升压电路，升压至1.4V仅需3时钟周期。

0.18μm CMOS, 0.5V-1.4V, 60pJ

DRAM字线升压低功耗0.5V工作高速升压

▸创新点1：电路创新 - 提出了一种适用于0.5V超低电压工作的DRAM字线升压电路，解决了传统SRAM在低电压下难以稳定工作的问题，显著降低了LSI的功耗。

▸创新点2：方法创新 - 通过理论分析和实验验证，实现了在3个时钟周期内快速升压至1.4V，满足了DRAM单元电容充电所需的电压，提升了DRAM的访问速度。

▸创新点3：性能创新 - 在保持电路面积不变的情况下，将升压时间和功耗分别降低了38%和68%，显著提高了电路的能效比和响应速度。

▸创新点4：工艺创新 - 采用0.18μm标准CMOS工艺成功制造了该升压电路，并通过实验验证了其高速升压的性能，展示了其在嵌入式及分立DRAM中的应用潜力。

Abstract

Al o wp o w e rh i g h - s p e e dw o r d - l i n eb o o s t e ri sp r o p o s e d for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage ( ) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on .W h e nt h e0 . 5V is adopted, widely used RAM, SRAM is dif ﬁcult to operate because the SRAM is sen- sitive to the variation. DRAM has a potential to operate at such low . As the key technology to realize