A0 . 5VO p e r a t i o n Loss Compensated DRAM Word-Line Booster Circuit for Ultra-Low Power VLSI Systems Shuhei Tanakamaru, Student Member , IEEE

Abstract

Al o wp o w e rh i g h - s p e e dw o r d - l i n eb o o s t e ri sp r o p o s e d for 0.5 V operation embedded and discrete DRAMs. To realize the low power LSIs it is important to decrease the supply voltage ( ) to e.g., 0.5 V because the active power consumption of LSIs strongly depends on .W h e nt h e0 . 5V is adopted, widely used RAM, SRAM is dif ficult to operate because the SRAM is sen- sitive to the variation. DRAM has a potential to operate at such low . As the key technology to realize 0.5 V operation DRAM, this paper proposes the wor d-line booster circuit. The the- oretical equation of the output voltage and the energy consump- tion of the proposed booster is extensively investigated. The pro- posed booster outputs 1.4 V in 3 clock cycles, which is shorter than the DRAM access time and the power consumption is 60 pJ. 1.4 V is the required word-line vol tage to successfully charge the DRAM cell capacitor. Compared with the conventional boosters, the rising time and the power consumption are decreased to 38% and 68%, respectively, with the same circuit area. The proposed circuit was fabricated with the 0.18 m standard CMOS process and the high-speed boosting is ex perimentally demonstrated.