A2 . 4 - V 60-Gb/s CMOS Driver With Digitally V ariable Amplitude and Pre-Emphasis Control at Multiple Peaking

Abstract

The design of a 60-Gb/s CMOS driver with input signal retiming is analyzed theoretically and validated exper- imentally. The output stage employs a modi fied distributed amplifier (DA) architecture with summation of both low-pass and reactively coupled bandpass signal paths along a 50- output transmission line. The DA featu res digital variable gain ampli fier (DVGA) cells to achieve broadband waveshape control with adjustable pre-emphasis at thre e different peaking frequencies. Binary-weighted MOSFET gate- finger groupings are employed in a Gilbert-cell based DVGA topol ogy to minimize bit-dependent output impedance and group delay variations. -parameter measurements of the retimed driver show 54-dB gain, while the standalone DA exhibits approximately 10 dB of peaking control in each of the three frequency bands. Input and output return loss is better than 10 dB up to 60 GHz. The circuit operates from 1.2- and 2-V supplies and achieves a throughput ef ficiency of 12.2 mW/Gb/s. Equalization exper iments at 40 Gb/s demonstrate compensation of various channel characteristics, including over 12 feet of cascaded coaxial cables with 21 dB loss at 20 GHz.