A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS Y ahya M. Tousi, Member , IEEE

Abstract

A delay-line-based analog-to-digital converter for high-speed applications is introduced. The ADC converts the sampled input voltage to a delay that controls the propagation velocity of a digital pulse. The output digital code is generated based on the propagation length of the pulse in a fixed time window. The effects of quantization noise, jitter, and mismatch are discussed. We show that because of the averaging mechanism of the delay-line, this structure is more power ef ficient in the presence of noise and mismatch in deep sub-micron CMOS. To show the feasibility of this approach, a 4 bit 1.2 GS/s ADC is d e s i g n e da n df a b r i c a t e di n6 5n mC M O Si na na c t i v ea r e ao f 110 m 105 m. The measured INL and DNL of the ADC are below 0.8 bits and 0.5 bits and it achieves an SNDR of 20.4 dB at Nyquist rate. This del ay-line-based ADC consumes 2m Wo f power from a 1.2 V supply resulting in 196 fJ/conversion step without using any calibra tion or post-processing.