A Scalable Massively Parallel Processor for Real-Time Image Processing Takashi Kurafuji, Masaru Haraguchi

Abstract

This paper d escribes a high performance scalable massively parallel single-instruction multiple-data (SIMD) pro- cessor and power/area ef ficient real-time image processing. The SIMD processor com bines 4-bit processing elements (PEs) with SRAM on a small area and thus enables at the same time a high performance of 191 GOPS, a high power ef ficiency of 310 GOPS/W, and a hig ha r e ae f ficiency of 31.6 GOPS/mm .T h e applied pipeline architecture is optimized to reduce the number of controller overhead cycles so that the SIMD parallel processing unit can be ut ilized during up to 99% of the operating time of typical application programs. T h ep r o c e s s o rc a nb ea l s oo p t i - mized for low cost, low power, and high performance multimedia system-on-a-chip (SoC) solutions. A combination of custom and automated implementation techn iques enables scalability in the number of PEs. The processor ha s two operating modes, a normal frequency (NF) mode for higher power ef ficiency and a double frequency (DF) mode for higher performance. The combination of high area ef ficiency, high power ef ficiency, high performance, and t he flexibility of the SIMD processor described in this paper expands the application of real -time image processing technology to a variety of electronic devices.