An Ultra-Low V oltage, Low-Noise, High Linearity 900-MHz Receiver With Digitally Calibrated In-Band Feed-Forward Interferer Cancellation in 65-nm CMOS

Abstract

We present an ultra-low voltage, highly linear, l ow noise integrated CMOS receiver operating from a 0.6-V supply. The receiver incorporates progr ammable, in-band feed-forward interferer cancellation at the baseband to obtain high l inearity and low noise operation at ultra-low supply voltages. Being able to reject adjacent channel or far-out blockers, the digitally cal- ibrated interferer cancellation improves the II P and IIP by more than 13 dB and 8 dB respecti vely with very little impact on the receiver noise figure. As such, it breaks the trade-off between linearity and noise figure, making it possible t o use a high-gain RF front-end to achieve low noise figure without affecting the linearity of the ultra-low voltage baseband circuits. The 0.6-V 900-MHz direct-conversion receiver prototype inte grates a differential LNA, RF transconductors, linea r quadrature current driven passive mixers, feed-forward inter ferer cancellation circuits, base- band variable gain transimpedance am plifiers and second-order channel-select filters. It has a nominal conversion gain of 56.4 dB, noise figure of 5 dB, IIP of 9.8 dBm and IIP of 21.4 dBm. The receiver operates reliably from 0.5 5–0.65 V , consumes 26.4 mW a n do c c u p i e sa na c t i v ea r e ao f1 . 7m min a 65-nm low-power CMOS process, of which the feed-forward interferer cancellation circuits consume 11.4 mW and oc cupies 0.43 mm .