← 返回 JSSC 论文列表JSSC 2011第10期RF & Wireless0.13μm CMOSNeural Network Accelerator
Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers
提出一种数字辅助自校准技术，提升直接转换接收器的二阶输入截点性能。
IIP2 >60 dBm, 转换增益38.5 dB, 噪声系数2.6 dB, IIP3 17.6 dBm, 15 mA@1.5V
直接转换接收器IIP2校准数字辅助CMOS低噪声
▸数字辅助自校准技术：通过数字信号处理实现IIP2校准，显著提升接收器的线性度（IIP2 >60dBm），无需外部滤波器，属于系统级创新。该方法在保证性能的同时降低了硬件复杂度。
▸低功耗低噪声设计：采用1.5V供电的CMOS工艺，仅消耗15mA电流，实现2.6dB的低噪声系数和38.5dB的转换增益，属于电路级创新。该设计在功耗和噪声性能之间取得了优异平衡。
▸最小硬件开销提升性能：通过数字辅助技术优化模拟/RF性能，仅增加1.56mm²的芯片面积（0.13μm工艺），属于方法创新。证明了数字处理可以高效补偿模拟缺陷。
▸集成化前端设计：在不使用LNA和混频器间外部滤波器的情况下实现高性能，展示出高度集成的接收器架构创新，为直接转换接收机设计提供了新思路。
Abstract
A robust digitally assisted self-calibration technique is presented to improve the input-referred second-order-intermod- ulation intercept point (IIP ) of direct-conversion receivers. The low-power, low-noise 1.8-GHz CM OS receiver prototype relies on digital signal processing to imp rove analog/RF performance with only a minimum hardware overhead and with no performance penalties on the RF front end and analog baseband. The RF front end achieves an IIP better than 60 dBm without external filters between the LNA and downconversion mixers, has a conversion gain of 38.5 dB, a low DSB noise figure of 2.6 dB, and an IIP of 17.6 dBm. It consumes 15 mA from a 1.5-V supply, and occupies 1.56 mm on a 0.13- m CMOS process.