A 12-bit, 45-MS/s, 3-mW Redundant Successive- Approximation-Register Analog-to-Digital Converter With

Abstract

This paper presents a sub-radix-2 redundant ar- chitecture to improve the perfo rmance of switched-capacitor successive-approximation-register (SAR) analog-to-digital con- verters (ADCs). The redundancy n ot only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A per- turbation-based digital calibration technique is also described that closely couples with the arc hitecture choice to accomplish simultaneous identi fication of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) an d a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-m W power from a 1.2-V supply and occupying 0.06-mm silicon area in a 0.13- m CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.