← 返回 JSSC 论文列表JSSC 2011第11期Data Converters0.13 μmSAR ADC
A 12-bit 45-MSs 3-mW Redundant Successive- Approximation-Register Analog-to-Digi
提出一种亚基数2冗余架构SAR ADC，通过数字校准技术提升性能并降低功耗。
12-bit, 45 MS/s, 3.0 mW, 1.2V, 0.06 mm²
SAR ADC冗余架构数字校准电容失配低功耗
▸亚基数2冗余架构提升SAR ADC性能
▸数字校准技术校正电容失配
▸减小采样电容以节省功耗和面积
Abstract
This paper presents a sub-radix-2 redundant ar-
chitecture to improve the perfo rmance of switched-capacitor
successive-approximation-register (SAR) analog-to-digital con-
verters (ADCs). The redundancy n ot only guarantees digitally
correctable static nonlinearities of the converter, it also offers
means to combat dynamic errors in the conversion process, and
thus, accelerating the speed of the SAR architecture. A per-
turbation-based digital calibration technique is also described
that closely