← 返回 JSSC 论文列表JSSC 2011第11期Data Converters0.13μmDelta-Sigma ADCDAC
A 20-MHz Bandwidth Continuous-Time Sigma-Delta Modulator With Jitter Immunity Improved Full Clock Period SCR (FSCR) DAC and High-Speed DW A Jun-Gi Jo, Student Member , IEEE, Jinho Noh, and Changsik Y oo , Member , IEEE
采用0.13微米CMOS工艺实现20MHz带宽连续时间ΣΔ调制器，通过全时钟周期开关电容电阻DAC提升时钟抖动免疫性。
63.9dB峰值信噪失真比, 68dB动态范围, 58mW功耗@1.2V
连续时间ΣΔ调制器时钟抖动免疫数据加权平均主动RC滤波器CMOS工艺
▸全时钟周期开关电容电阻DAC反馈技术
▸新型数据加权平均技术消除640MHz时钟时序瓶颈
▸第三阶主动RC环路滤波器设计
Abstract
A 20-MHz bandwidth continuous-time (CT) sigma- delta modulator (SDM) with third-order active-RC loop filter and 4-bit quantizer is implemented in a 0.13- m CMOS process. The immunity to clock jitter is greatly improved by employing full clock period switched-capacitor-resis tor (FSCR) digital-to-analog con- verter (DAC) for feedback. A new data weighted averaging (DW A) technique is developed to remove the timing bottleneck at 640 MHz clock frequency. The CT SDM achieves 63.9 dB peak signal-to- noise-and-distortion ratio (SNDR) and 68 dB dynamic range (DR) which decreases by only 2.3 dB when the RMS jitter of the 640 MHz clock is 15.6 ps. The power consumption is 58 mW from a 1.2-V supply.