JSSC 2011第11期Clocking & PLLs28nmSRAM

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb

提出一种检测双端口SRAM最差工作电压的电路技术，显著提升测试效率。

28nm CMOS, 512-kb DP-SRAM

双端口SRAM工作电压检测测试效率异步时钟28nm工艺

▸创新点1：提出了一种检测最差工作电压的电路技术，通过异步时钟操作下的检测机制，显著提升了测试效率。

▸创新点2：设计了异步时钟操作下的最差Vmin检测电路，解决了传统测试方法耗时且成本高的问题，实现了400倍测试速度提升。

▸创新点3：开发了一种针对写读干扰的筛选电路，能够在28 nm低功耗CMOS技术下精确检测最差Vmin，实验验证误差小于6%。

▸创新点4：通过512-kb双端口SRAM宏的设计与制造，验证了所提电路技术的可行性和高效性，为大规模SRAM测试提供了新方法。

Abstract

Showing that the worst minimum operating voltage (Vmin) of an 8T dual-port (DP) SRAM is determined by the write/ read-disturbing condition with a ﬁnite clock skew, we propose a cir- cuit technique to detect the worst Vmin in asynchronous clock op- eration. This circuitry allows us to screen the worst bit in an array that is conventionally obtained by a costly and time-consuming test procedure. For instance, we can a t least realize 400x speed-up for the test time compared to the conventional met