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JSSC 2011第11期RF & Wireless65nmEqualizer

A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band Ji-Hoon Park,S t u d e n tM e m b e r ,I E E E

设计了一种用于60 GHz频段的数字LOS/NLOS均衡器,支持2 Gb/s数据传输,功耗56 mW。
65nm CMOS, 2 Gb/s, 5.6 mW
60 GHz数字均衡器分布式算术Golay相关器WPAN
创新点1:并行分布式算术(DA)架构 - 该方法创新通过并行化计算显著降低了功耗,实现了在65 nm CMOS工艺下仅消耗56 mW功率,支持2 Gb/s的高数据速率,优化了数字均衡器的能效比。
创新点2:可配置的前馈和反馈均衡器 - 该电路创新采用6抽头前馈和32抽头反馈结构,可灵活配置以抵消长达72符号的信道响应,适应LOS和NLOS多种信道条件,满足IEEE WPAN标准要求。
创新点3:基于Golay相关器的信道估计器 - 该系统创新利用Golay序列的高相关性,精确估计信道系数、频率和定时误差,为均衡器提供快速准确的参数配置,提升了系统整体性能。
创新点4:65 nm CMOS工艺实现 - 该工艺创新将2 mm²的测试芯片集成于65 nm CMOS技术中,实现了高集成度和低功耗的平衡,为60 GHz频段PANs提供了实用的硬件解决方案。
Abstract
T h ew i d eu n l i c e n s e db a n d width of a 60 GHz channel presents an attractive opport unity for high data rate and low power personal area networks (PANs). The use of single-carrier modulation can yield energy-ef ficient transmitter and receiver implementation, but equalization of the long channel response in non-line-of-sight (NLOS) conditions presents a signi ficant chal- lenge. A digital equalizer for 60 GHz channels has been designed for both line of sight (LOS) and NLOS channel conditions to meet the IEEE WPAN standard. Power consumption is minimized by using a parallelized distribute d arithmetic (DA) architecture. A2m m 2m mt e s tc h i pi n6 5 n mC M O Si m p l e m e n t sa6t a p feedforward and 32 tap feedback equalizer that can be con figured to cancel the response of up to 72 symbols, and consumes 5.6 mW at 2 Gb/s throughput. The chip als o includes a channel estimator based on a Golay correlator for setting the equalizer coef ficients and estimating frequen cy and timing error.