Characterization of Dynamic SRAM Stability in 45 nm CMOS

Abstract

Optimization of SRAM yield using dynamic stability metrics has been evaluated in the past to ensure continued scaling of bitcell size and supply voltage in future technology nodes. Var- ious dynamic stability metrics have been proposed but they have not been used in practical failure analysis and compared with con- ventional static margins. This work compares static and dynamic metrics to identify expected correlations. A dynamic stability char- acterization architecture using pulsed word-lines