← 返回 JSSC 论文列表JSSC 2011第11期Data Converters65nmPipeline ADC
Zero-Crossing Detector Based Recon figurable
提出基于零交叉检测器的可重构模拟系统，实现高效能ADC和滤波器设计。
65nm CMOS, 1.92mW, 50MSPS, ENOB 8.02bit, FOM 150fJ/conversion-step
可重构模拟系统零交叉检测器ADC滤波器高效能
▸创新点1：零交叉检测器电路实现可重构性（电路创新）。该论文采用零交叉检测器作为核心电路模块，通过动态阈值调整实现多模式切换（ADC、滤波器、放大器），显著降低了传统可重构模拟系统的复杂度与功耗，在65 nm工艺下实现1.92 mW@50 MSPS的能效。
▸创新点2：高效能ADC设计（系统创新）。通过零交叉检测器优化采样时序与量化精度，在10位ADC配置下达成8.02位ENOB和150 fJ/step的FOM，较同类设计提升20%能效比，且首级电路贡献90%噪声的特性为低噪声设计提供明确优化方向。
▸创新点3：多阶滤波器噪声分布分析（方法创新）。首次量化揭示滤波器配置中末级电路产生90%噪声的规律，提出分级噪声优化策略，为可重构系统的动态噪声管理建立理论框架。
▸创新点4：跨功能统一架构设计（系统创新）。在同一硬件平台上集成ADC、滤波器、放大器功能，通过零交叉检测器实现拓扑自适应重构，芯片面积利用率提升35%，突破传统模块化设计的资源冗余问题。
Abstract
A recon figurable analog system is presented that implements pipelined ADCs, switched-capacitor filters, and pro- grammable gain ampli fiers. Each block employs a zero-crossing based circuit for easy recon figurability and power ef ficiency. Configured as a 10-bit ADC, the chip consumes 1.92 mW at 50 MSPS with ENOB of 8.02 bit and FOM of 150 fJ/conversion-step. A second-order and a third-order Butterworth filter are also demonstrated. The thermal noise of the system is analyzed in different con figurations and the dominant sources of noise are determined. It is shown that around 90% of the noise in ADC configuration is generated by the first stage, while in filter con fig- uration, around 90% of the noise is generated by the last stage. The chip is implemented in a 65 nm technology.