A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration Amr Elshazly, Student Member , IEEE, Rajesh Inti , Student Member , IEEE, Wenjing Yin, Student Member , IEEE, Brian Young, Student Member , IEEE, and Pavan

Abstract

A digital phase-locked loop (DPLL) employs noise cancellation to mitigate performance degradation due to noise on the ring oscillator supply voltage. A deterministic test signal-based digital background calibration is used to accurately set the cancellation gain and thus achieve accurate cancellation under different process, voltage, temperature, and operating frequency conditions. A hybrid, linear proportional control and bang–bang digital integral control, is used to obviate the need for a high-reso- lution time-to-digital converter and reduce jitter due to frequency quantization error. Fabricated in 0.13 m CMOS technology, the DPLL operates from a 1.0 V supply and achieves an operating range of 0.4-to-3 GHz. At 1.5 GHz, the DPLL consumes 2.65 mW power wherein the cancellation circuitry consumes about 280 W. The proposed noise cancellation scheme reduces the DPLL’s peak-to-peak jitter from 330 to 50 ps in the presence of a 30 mV /112/112 10 MHz supply noise tone, and the DPLL peak-to-peak jitter is 50 ps in the absence of any supply noise. The DPLL occupies an active die area of 0.08 mm /50, of which the calibration logic and cancellation circuitry occupy only 12.5%.