A 04-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using D

Abstract

A digital phase-locked loop (DPLL) employs noise cancellation to mitigate performance degradation due to noise on the ring oscillator supply voltage. A deterministic test signal-based digital background calibration is used to accurately set the cancellation gain and thus achieve accurate cancellation under different process, voltage, temperature, and operating frequency conditions. A hybrid, linear proportional control and bang–bang digital integral control, is used to obviate the need for a hig