← 返回 JSSC 论文列表JSSC 2011第12期Clocking & PLLs0.13μmNeural Network Accelerator
A 05-to-25 Gbs Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acq
一种无参考、高数字化的半速率时钟数据恢复电路，具有改进的输入占空比误差容忍度。
0.5-2.5 Gb/s, 6.1 mW @ 2 Gb/s, 1.2V
时钟数据恢复无参考半速率数字频率锁定环占空比校准
▸使用分频器链生成已知子谐波音调
▸数字频率锁定环驱动振荡器至输入数据频率的任意子速率
▸时钟相位校准可校正高达20%的输入数据占空比误差
Abstract
A reference-less highly digital half-rate clock and data
recovery (CDR) circuit with improved tolerance to input duty cycle
error is presented. Using a chain of frequency dividers, the pro-
posed frequency detector produces a known sub-harmonic tone
from the incoming random data. A digital frequency-locked loop
uses the extracted tone, and drives the oscillator to any sub-rate
of the input data frequency. The early/late outputs of a conven-
tional half-rate bang-bang phase detector are used to d