A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance Rajesh Inti, Student Member , IEEE, Wenjing Yin , Student Member , IEEE, Amr Elshazly , Student Member , IEEE, Naga Sasidhar, and Pavan

Abstract

A reference-less highly digital half-rate clock and data recovery (CDR) circuit with improved tolerance to input duty cycle error is presented. Using a chain of frequency dividers, the pro- posed frequency detector produces a known sub-harmonic tone from the incoming random data. A digital frequency-locked loop uses the extracted tone, and drives the oscillator to any sub-rate of the input data frequency. The early/late outputs of a conven- tional half-rate bang-bang phase detector are used to determine the duty-cycle error in the incoming random data and adjust the oscillator clock phases to maximize receiver timing margins. Fabri- cated in 0.13 m CMOS technology, the prototype digital CDR op- erates without any errors from 0.5 Gb/s to 2.5 Gb/s. At 2 Gb/s, the prototype consumes 6.1 mW power from a 1.2 V supply. The pro- posed clock-phase calibration is capable of correcting upto 20% of input data duty-cycle error.